The dramatically increasing integration density of modern semiconductor components such as microprocessors or logic chips is necessarily accompanied by an increase in the number and density of connecting input/output (I/O) terminals on the chip. Modules capable of accommodating chips with more than 400 terminals are already known. However, the footprint of such devices is significantly greater than that of previously used components. The requirements on critical signal delay times within data processing systems, however, increasingly demand ever shorter minimum distances between critical chips.
It is possible to satisfy these requirements by mounting a number of chips on complex multi-chip modules thereby making the distances between critical chips extremely small.
It would, however, be preferable to solder the chips directly onto the circuit board using direct chip attach (DCA) processes, as this would make an entire packaging level superfluous and consequently it would be possible to achieve considerable cost savings in addition to the reduced signal delays. In this event, however, the conducting line widths and spacings and the corresponding through holes close to the chip must be considerably smaller than is feasible with conventional printed circuit board technology.
A series of proposals for the solution of this problem have been made, for instance, one example being to use what is referred to as a surface laminar circuit (SLC) process, in which chips may be soldered directly to the contacts of the board through two thin film layers on the surface of a conventional printed circuit board. This manufacturing process is relatively complex and demands relatively costly registration and smoothing procedures.